Surabhi Agarwal

Surabhi Agarwal

Impact-driven technology professional with 8+ years across semiconductor and agri spaces. Skilled in product strategy, digital transformation, and cross-functional leadership, delivering innovative solutions and aligning technology with business goals for scalable, sustainable growth.

Work Experience:

8.8 Years

Industry:

Agriculture & Food Processing | Manufacturing & Engineering | Technology

Function:

Entrepreneurship | Project & Program Management | Software Engineering

Work Experience

Farm Native India (Social Impact startup creating sustainable livelihoods in the Northeast) | Bengaluru/Assam

  • Co-Founder
    • Handled product, tech & business development of a profitable, bootstrapped social enterprise with a topline of $150K.
    • Pioneered a sustainable livelihood model for remote farmers with a 3-member team, boosting revenue/kg by 80%. Led a millet cultivation pilot with 500+ farmers, initiating workshops to support crop and product development.
    • Launched a B2B direct-buying agribusiness, buying from farmers and supplying to 10+ B2B and govt. clients
    • Secured strategic partnership to build traceable supply chain, negotiated a deal with 81% reduction in costs.
    • Developed a sustainable wooden homeware collection using locally sustainably sourced Teak wood to balance operational challenges in scaling agricultural production, expanding Farm Native’s market and revenue sources.
       

Intel Corporation, Bengaluru

  • Product Development Engineer
    • Led a digital transformation initiative to build a data-driven platform that automated planning, ordering, and tracking of ~10,000 validation boards across 10+ labs, improving accuracy and eliminating manual effort, enabling ~$1M annual savings.
    • Managed end-to-end product lifecycle with a 3-member team (covering UX design, database architecture, backend logic) while aligning with 15+ global teams under tight delivery timelines.
    • Conducted focus groups with 100+ stakeholders to define requirements, identify use cases, and drive adoption across multiple Intel business units.
    • Built a reusable QA and documentation framework adopted by 5+ projects, improving issue traceability and release quality; appointed QA lead for 10+ team projects.
    • Drove adoption of across 3+ internal organizations, promoting integration and usage through internal conferences
    • Co-developed a concept for ML-based debug automation, collaborating with data science and platform architects to enhance debug efficiency by 20%
       
  • Software Engineer (Grade 6, Grade 5)
    • Drove validation planning and execution for Intel’s Lakefield (first Foveros chip) and Alder Lake (12th Gen) platforms, ensuring alignment of priorities across multiple milestones and resolving critical issues impacting customer timelines
    • Directed stress and stability validation on ~40 systems, coordinating a 10-member team in meeting rigorous quality standards, and providing progress visibility to senior leadership through structured reporting and risk management
    • Drove execution under resource constraints during site shutdowns and COVID-19 by reallocating lab resources, optimizing workflows, and maintaining milestone readiness for high-pressure launches
    • Partnered with 40+ global stakeholders across engineering domains to influence validation scope, resource planning, and issue prioritization, enabling successful delivery of 10+ product milestones
    • Represented Intel in a critical debug engagement with Samsung (Seoul), resolving high-impact issues that unlocked Beta milestone for Galaxy Book S launch
    • Developed a Python based automation script to standardize validation process, reducing turnaround time by 50% and accelerating issue resolution on Lakefield Platform
    • Mentored new team members on workflows and tools, improving team efficiency and fostering cross-functional trust
       

Artesyn Embedded Technologies, Hyderabad

  • Software Engineer
    • Assumed ownership of the flagship product’s diagnostics software (ViewCheck) within six months, driving a 70% reduction in software bugs and improving product reliability.
    • Implemented a network virtualisation feature in half of the budgeted time, meeting customer requirements and enhancing system performance.
    • Delivered system software for critical PCIe host/endpoint cards collaborating with a 20-member cross-functional team, enabling seamless functionality and on-time launch of the flagship platform.
    • Resolved high-priority customer-reported issues on legacy platforms, reducing defects by 30% through diligent debugging and issue tracking.
Accomplishments
  • SIV Superstar Award (Q2 2020) for efforts to remove ship blockers to get Lakefield Samsung SpaceX launched
  • Department Team Award (Q1 2020) for Lakefield Platform Stability Debug & Engineering Excellence
  • Spontaneous DRA (Q1 2019) for persistent efforts in enabling Power Management features and stabilizing core/package C-states (standby, sleep), Warm Reset (restart), and S4/S5 (hibernate/shutdown) in Lakefield A silicon step
  • Promoted within 1.5 years from Grade 5 to Grade 6 in recognition of continued impact and potential for leadership
  • Chosen to represent the System Integration & Validation organization (~200 members) at a critical 2-week customer workshop for Samsung in Seoul that enabled the Beta milestone for the Lakefield-based Galaxy Book S (Space-X)
  • Recognized by global stakeholders for One Intel mindset, consistently aligning teams on issue resolution under tight timelines. Commended by senior leadership for cross-functional coordination, customer-first attitude, and outcome ownership across both Lakefield and Alder Lake product cycles. Praised for ownership and leadership during resource shortages, particularly during Alder Lake Power-On with minimal staff and high-priority issues
  • Top 5 among the finalists in org-wide innovation challenge for co-ideating an ML-powered debug assistant, projected to improve triage efficiency by 10%; translated concept into business model and technical feasibility framework
Education
  • B. Tech. (Electronics and Communication Engineering) – Tezpur University, Assam | India
Certification
  • Lean Six Sigma Certification - Green Belt (Level II) - KPMG
  • Product Management (HelloPM)
  • Product Led Growth (The Product Folks)
Extra-curricular
  • Vertical Head (Startups & Niche), Placement Committee at IIMA PGPX
  • Member, Profile Committee at IIMA PGPX
    • Curated and managed 5 LinkedIn features on “PGPX Voice” showcasing impactful stories
  • Part of cycling communities in Bangalore and at Intel undertaking 50+ rides; Completed multiple 100-200 km solo/group rides. Delivered essentials to the elderly and indisposed on bicycle in Bengaluru during Covid-19 pandemic. (2018 – present)
  • Turned my mother’s passion of making handmade candles to custom candle creation business; fulfilled 100+ orders (2023 – 2024)
  • Certified Mental Health First Aider: enabled safe spaces (listening circles) on mental health at Intel (2022 – 2023)
  • University Hostel management - Aug 2013 to May 2014 - Assistant Prefect: Ensured the welfare of 200+ boarders, mentoring and supporting in inter-hostel parades/competitions, resolving conflicts and fostering a sense of community.
  • National Cadet Corps- 2011-13 - Cadet (level 'B'): Organised and participated in institutional training, national camps and community service fostering discipline, leadership, and a strong sense of social responsibility
  • University Placement cell - Aug 2014 to June 2015 - Coordinator: Facilitated on and off campus recruitments for 2015 Engineering batch