Debug team lead | Intel India Pvt Ltd | Bengaluru, India
Strategy
- Led the strategic preparation and execution of hardware accelerators on Intel’s Xeon6 server processor launch, addressing 5+ critical gaps in the test strategy, conducting pilot testing 8 weeks ahead of schedule, and reducing lab failures by 30%, ensuring successful market entry
- Developed and implemented a Python-based automated debug and analytics framework across 10+ teams, reducing root cause analysis (RCA) time by 25%, streamlining issue resolution, and achieving significant cost savings
- Collaborated with global teams across the US, EU, India, and China to prototype and execute 25+ RCA strategies for complex end-user cases, resolving key technical challenges and improving product launch readiness by 20%
Leadership
- Led the resolution of 15+ critical product issues and provided subject matter expertise on 10+ high-impact challenges, ensuring the on-time delivery of prototypes for tier-1 customers during key product launch phases
- Facilitated weekly R&D brainstorming and deep-dive technical sessions, driving knowledge sharing and upskilling within the department, while coordinating research efforts with global SMEs that resulted in 3 IEEE conference publications in 2 quarters
- Mentored and onboarded a new cohort of interns, designing a comprehensive 6-week training plan to develop functional expertise and successfully integrating them into cross-functional teams
Innovation
- Innovated an Azure-based real-time telemetry data collection and analysis platform, scaling an existing RCA software stack and increasing virtualization test coverage by over 30%, as part of Intel’s Innovation Days initiative
- Co-developed an ML-powered defect prediction mechanism that boosted operational efficiency by 20% across Xeon6 derivative products, significantly enhancing defect detection accuracy
- Pioneered a pre-production verification process for complex features, reducing testing time from 10+ weeks to 4 weeks and co-authored 2 research papers that improved pre-production test coverage by 10% on Intel Xeon6 servers
Design and Verification lead | Intel Corporation | California, USA
Product development
- Developed the feature roadmap for 15+ debug features and implemented a scalable design architecture across 3 Xeon6 product families, ensuring alignment with product goals and technical requirements
- Led the design, development, and implementation of a Python-based automation tool for design integration, improving design quality by 40% and reducing integration time by 50% on multiple Xeon product variants
- Managed the full software development lifecycle (SDLC) for a pre-production verification tool, onboarding 40+ global teams and ensuring zero defects in debug features across 3 Xeon product generations through rigorous testing and design reviews
Cross-functional collaboration
- Collaborated with the tools team to overhaul the pre-production verification infrastructure for Intel Rivercrest (AI training processor), accelerating the production schedule by 3 weeks and ensuring smoother transitions across functions
- Led cross-functional efforts with hardware, design, and verification teams to influence 5 architectural changes, reducing pre-production defects by 30% and aligning technical execution with product goals
- Worked with 10+ global teams post-NetSpeed acquisition, consolidating verification tools to enhance operational efficiency by 20%, improving pre-production workflows and meeting evolving requirements across multiple organizations
Project Management
- Managed the full lifecycle of 25+ Xeon6 debug features from conception to release, overseeing resource planning, development timelines, and testing schedules across technical teams to ensure timely project delivery
- Built and maintained a comprehensive pre-production quality tracker for debug features on Intel Rivercrest, conducting design reviews and ensuring alignment with project milestones, contributing to smooth project execution and meeting production schedule